1. Field of the Invention
The present invention relates to a magnetic memory device and a method for manufacturing the magnetic memory device. More specifically, the present invention relates to a nonvolatile magnetic memory device for storing information by utilizing a change in resistance depending on whether spin directions of ferromagnetic materials forming a tunnel magneto resistance element are parallel or antiparallel. The present invention also relates to a method for manufacturing the nonvolatile magnetic memory device.
2. Description of the Related Art
With a remarkable popularization of information communication apparatuses, especially personal small-sized apparatuses such as mobile terminals, there has been a demand for higher performance including higher integration levels, higher speed and a lower power consumption on memory devices, logic elements and other components of those apparatuses. In particular, a nonvolatile memory is seen as an indispensable device that aims at meeting the needs of a ubiquitous networking technological era.
Even when power is reduced, an abnormality occurs, or a connection with a server or a network occurs due to a problem of some sort, for instance, a nonvolatile memory would be able to protect personal valuable information. Accordingly, an approach to a nonvolatile memory of higher-density, larger-capacity becomes increasingly significant as technologies for replacing hard disks or optical disks face an intrinsic limitation for the downsizing due to the presence of movable parts in those apparatuses.
In addition, recent mobile apparatuses have been designed to hold down power consumption as much as possible in such a way as to place unnecessary circuits blocked in a standby mode. However, if a nonvolatile memory combining a high-speed network memory and a large-capacity storage memory is attainable, a waste in power consumption and waste of memory capacity may be reduced. Further, a realization of a higher-speed larger-capacity nonvolatile memory may provide a so-called instant-on function that enables a startup almost in the instant the power is applied.
Examples of the nonvolatile memory include a flash memory employing a semiconductor, a FRAM (Ferroelectric Random Access Memory) employing a ferroelectric material and others. However, the flash memory has a disadvantage of a slow writing operation because of a writing rate as low as the level of μ (micro) seconds. A problem with the FRAM presents is that the number of times information is erasable is limited to a range of 1012 to 1014, which leads to a low endurance that is not enough to replace the FRAM with a static random access memory or a dynamic random access memory completely. The FRAM also involves a problem in that it is difficult to fabricate a ferroelectric capacitance by etching.
A memory that is attractive as a candidate for a nonvolatile memory free from the above drawbacks is a magnetic memory called a MRAM (Magnetic Random Access Memory). Early MRAMs are of a type that is based on a spin valve realized with an AMR (Anisotropic Magneto Resistive) effect and/or a GMR (Giant Magneto Resistance) effect. The AMR effect has been reported in “Thin Solid Films” Vol. 216(1992), pages 162 to 168, by J. M. Daughton. The GMR effect has been reported in “IEDM Technical Digest” (1997), pages 995 to 997, by D. D. Tang et al. However, the MRAM has had a disadvantage of a high power consumption per bit at the time of reading because of a loaded memory cell resistance as low as 10 Ω to 100 Ω, resulting in a difficulty in ensuring larger capacity.
In addition, as reported in “Physics Reports” Vol. 238 (1994), pages 214 to 217, by R. Meservey et al, a TMR (Tunnel Magneto Resistance) effect has had a limitation in resistance change rate to a range of 1% to 2% at room temperature. However, as having been reported in “J. Magnetism & Magnetic Material” Vol. 139 (1995), L 231, by T. Miyazaki et al, a resistance change rate as high as close to 20% has proved to be attainable with the TMR effect. Accordingly, the MRAM realized with the TMR effect has attracted much attention.
The MRAM has a simple structure enough to easily ensure a higher integration level. In addition, the MRAM is to store information with a magnetic moment rotation, so that it is expected to have a greater number rewriting. With respect to an access time, the MRAM is also expected to be accessible at a considerably high rate. Specifically, an accessibility of the MRAM at a rate of 100 MHz has been already reported in “ISSCC Digest of Technical Papers” (February 2000), pages 128 to 129, by R. Scheuerlein et al.
A MRAM of a conventional type that is composed of 1 switching element and one TMR element (of a 1T1J structure) will now be described with reference to FIG. 30 showing a cross-sectional view of a schematic configuration of the MRAM of the conventional type. In FIG. 30, there is shown an exemplary MRAM using a MOS transistor as a switching element.
As shown in FIG. 30, a silicon substrate 21 has thereon a MOS transistor 24 for the switching element. One end of an extraction electrode 137 of a TMR (Tunneling Magneto Resistance) element 13 is connected to one diffusion layer 28 of the MOS transistor 24 through a contact 30, a first landing pad 31, a contact 32, a second landing pad 33, a contact 34, a third landing pad 35 and a contact 36 that are stacked in ascending order. The other end of the extraction electrode 137 is connected to an anti-ferromagnetic layer 131 of the TMR element 13. The extraction electrode 137 is formed with a conductive material, for instance, and the anti-ferromagnetic layer 131, which will be described later, is used as the extraction electrode. Alternatively, the extraction electrode may be a part of the anti-ferromagnetic layer 131.
A sense line 15 is connected to the other diffusion layer 27 of the MOS transistor 24 through a contact 29 including a tungsten plug.
The TMR element 13 is configured with a tunnel barrier layer 133 interposed between a ferromagnetic layer forming a fixed magnetization layer 132 and a ferromagnetic layer forming a storage layer 134 that yields a relatively easy spinning of magnetization. The TMR element 13 also has the anti-ferromagnetic layer 131 that is in contact with a lower surface of the fixed magnetization layer 132. The TMR element 13 further has a cap layer 135 and an electrode layer 136 that are stacked on the storage layer 134, and a bit line 12 is connected to the electrode layer 136. A write word line 11 is provided beneath the extraction electrode 137 of the TMR element 13 through a fourth insulator film 44. The write word line 11 and the bit line 12 cross in a grade-separated manner with the TMR element 13 interposed therebetween.
The storage layer 134 and the fixed magnetization layer 132 are formed with, for instance, nickel, iron, cobalt, an alloy including at least two out of nickel, iron and cobalt and a ferromagnetic material mainly containing the above alloys. The fixed magnetization layer 132 is in contact with the anti-ferromagnetic layer 131, so that an interlayer exchange coupling between the fixed magnetization layer 132 and the anti-ferromagnetic layer 131 causes the fixed magnetization layer 132 to have an intensive unidirectional magnetic anisotropy.
The anti-ferromagnetic layer 131 may be formed with, for instance, one of an iron-manganese alloy, a nickel-manganese alloy, a platinum-manganese alloy, an iridium-manganese alloy, a rhodium-manganese alloy, a cobalt oxide and a nickel oxide.
The tunnel barrier layer 133 includes, for instance, an insulator material such as an aluminum oxide, a magnesium oxide, a silicon oxide, an aluminum nitride, a magnesium nitride, a silicon nitride, an aluminum oxy-nitride, a magnesium oxy-nitride and a silicon oxy-nitride. The tunnel barrier layer 133 plays a role of carrying a tunnel current while disconnecting a magnetic bond between the storage layer 134 and the fixed magnetization layer 132. These magnetic films and conductive films are formed typically using a sputtering method. The tunnel barrier layer 133 is obtainable by means of oxidation, nitridation or oxy-nitridation of a metal film having been formed by sputtering.
Further, the cap layer 135 provides functions such as a prevention of mutual diffusion between the cap layer 135 and an interconnection that is to connect the TMR element 13 with a different TMR element 13, a reduction in contact resistance and an anti-oxidation of the storage layer 134. Typically, the cap layer 135 is formed with a material such as copper, a tantalum nitride, tantalum and a titanium nitride.
An operation of the above-mentioned magnetic memory device is described next. In the TMR element 13, information is read by means of detecting a change of a tunnel current due to the magneto resistance effect, while the magneto resistance effect depends on orientations of magnetization of the storage layer 134 relative to the fixed magnetization layer 132.
A way to write data onto the TMR element 13 is to store “1” or “0” by changing a magnetization orientation of the storage layer 134 with a resultant magnetic field generated by applying a current to the bit line 12 and the write word line 11. Meanwhile, readout of information from the TMR element 13 is performed by means of detecting the change of the tunnel current due to the magneto resistance effect. When magnetization orientations of the storage layer 134 and the fixed magnetization layer 132 are parallel, a resistance is assumed to be low (a low resistance will be defined as “0”, for instance). On the other hand, when the magnetization orientations of the storage layer 134 and the fixed magnetization layer 132 are antiparallel, a resistance is assumed to be high (a high resistance will be defined as “1”, for instance).
An easy axis magnetic field (HEA) of the storage layer 134 is generated by a current passing through the bit line 12, while a hard axis magnetic field (HHA) of the storage layer 134 is generated by a current passing through the write word line 11.
An asteroid curve shown in FIG. 31 represents an inverted threshold value in the magnetization orientation of the storage layer with a generated easy axis magnetic field HEA and a generated hard axis magnetic field HHA. When a resultant magnetic field vector equivalent to parts A and B on the outside of the asteroid curve is generated, a field reversal occurs, which enables data to be stored. A resultant magnetic field vector equivalent to a part C on the inside of the asteroid curve causes no reversal of a cell from one of current bistable states thereof. In addition, magnetic fields individually generated from the word line and the bit line are also applied to cells other than that at a point of intersection between the word line and the bit line that are carrying a current. Thus, when the generated magnetic fields are more intensive than a unidirectional inverted magnetic field HK (or within a region B), magnetization orientations of the cells other than that at the point of intersection are also inverted. Accordingly, selective writing of information onto a selected cell is enabled only when the resultant magnetic field falls on a region A shown by slanted lines.
As described above, the MRAM is configured with an array of memory cells located at points of intersection of a lattice composed of the bit lines and the write word lines. In the case of the MRAM, asteroid magnetization reversal characteristics obtainable with the write word line and the bit line are typically utilized to store information selectively into individual memory cells.
A resultant magnetization in a single storage region is determined depending on how to combine vectors in the easy axis magnetic field HEA and the hard axis magnetic field HHA respectively applied to the single storage region. A current passing through the bit line applies the easy axis magnetic field (HEA) to the cells, while a current passing through the write word line applies the hard axis magnetic field (HHA) to the cells.
There are two main types of MRAMS. One is the MRAM composed of one switching element and one TMR element (of the 1T1J structure) as previously described with reference to FIG. 30. The other is a well-known cross-point MRAM as shown in FIG. 32.
As shown in FIG. 32, a cross-point MRAM 301 is obtainable with a configuration, in which a TMR element 313 and a pn-junction diode 314 are interposed between a write word line 311 and a bit line 312 that cross in a grade-separated manner. The TMR element 313 is configured with a tunnel barrier layer 333 interposed between two ferromagnetic layers 332 and 334 and also has an anti-ferromagnetic layer 331 connected to one ferromagnetic layer 332. The pn-junction diode 314 is located adjacent to the anti-ferromagnetic layer 331 and is composed of n pieces of layers connected together.
As shown in FIG. 33, a minimum size of a line width (or line interval) of each write word line 311 and each bit line 312 that are arrayed to meet a design rule is now assumed to be F. Then, the cross-point MRAM 301 would be obtainable in a cell area as much as 4F2. The cross-point MRAM requires no switching element for each TMR element 313, providing a memory that ensures a large capacity though being inferior in access rate.
Meanwhile, the MRAM cell composed of one switching element and one TMR element (of the 1T1J structure) as shown in FIG. 30 or a MRAM cell realized with two switching elements and two TMR elements (of 2T2J structure) of the above-mentioned MRAM cell in a complementary manner should be configured with the write word line electrically insulated from the TMR element, among two crossing lines of the write word line and the bit line. Thus, the fixed magnetization layer of the TMR element needs to be connected to the diffusion layer of the MOS transistor for the switching element by providing an extraction electrode, a contact hole and others in such a manner as to bypass the write word line located right beneath the TMR element.
In the MRAM composed of one switching element and one TMR element, when a minimum size of a line width (or line interval) of each write word line 11 and each bit line 12 that are arrayed to meet a design rule is assumed to be F, there is a limit to a cell size. Specifically, a minimum length required for a cell configuration is limited to 4F in a parallel direction to an array of the bit lines 12 and 2F in a parallel direction to an array of the write word lines 11, as shown in FIG. 34, for reason that there must be provided the TMR element 13 in a region between the write word line 11 and the bit line 12, and also the contact C that is to establish a connection between the bit line 12 and the diffusion layer (not shown) of the transistor for the switching element. Thus, a cell area as small as less than 8F2 is unobtainable. It is to be noted that the transistor for the switching element of the MRAM having the above configuration shown in FIG. 34 has a gate electrode 24 located on a lower lateral side of each write word line 11.